1. Field of the Invention
The present invention relates to a receiving circuit and a transmission/reception system utilizing the same, more particularly, to a receiving circuit reset upon reception of burst data in a transmission/reception system in which the burst data and a clock signal are transmitted at least from a transmitting unit to a receiving unit.
2. Description of Related Art
FIG. 1 is a block diagram showing a conventional transmission/reception system. The system includes a transmitting unit 102 and a receiving unit 104 containing a receiving circuit 106. The transmitting unit 102 transmits a burst data signal DATA0 and a clock signal CLK to the receiving unit 104. The receiving circuit 106 receives these signals and outputs a data signal DATA1 from these signals. The system is used in a computer system, for instance. In this case, a computer corresponds to the transmitting unit and a unit for receiving data from the computer corresponds to the receiving unit.
FIG. 2 is a block diagram showing the receiving circuit 106. The receiving circuit 106 includes a detector 114, a control unit 118, a buffer unit 122, and an output unit 124. All of these units are supplied with the clock signal CLK and operates in synchronously with the clock signal. The detector 114 receives the data DATA0 from the transmitting unit 102 to detect whether there is the burst data, and generates a signal DP indicating the presence of burst data when it is determined that the burst data is present. The buffer unit 122 also receives the data DATA0 from the transmitting unit 102 in response to a signal DRS from the control unit 118 to store it therein. Also, the buffer unit 122 generates a signal SD while the burst data is stored or held therein. The output unit 124 outputs the stored data from the buffer unit 122 as data DATA1 in response to a signal DOE from the control unit 118. The control unit 118 controls the detector 114, the buffer unit 122, and the output unit 124. More particularly, the control unit 118 receives the signal DP from the detector to generate the signal DRS indicating that the burst data is to be stored in the buffer unit 122. The control unit 118 generates the signal DOE in response to the signal SD from the buffer unit 122 and the signal DP from the detector 114.
FIG. 3 is a block diagram of the control unit 118. The control unit 118 includes a control logic unit 118-1 and a status register 118-2. The status register 118-2 stores the status of the receiving circuit 106 in response to the clock signal CLK. The control logic unit 118-1 generates the control signals DRS and DOE in accordance with the signals DP and SD and the current status stored in the register 118-2.
FIG. 4 is a state transition diagram of the receiving circuit 106. The receiving circuit 106 waits for burst data in the state S2. When the burst data is transmitted from the transmitting unit 102 to the receiving unit 104, the state changes to an on-reception state S4 because the detector detects the burst data to issue the signal DP to the control unit 118. When the transmission of burst data is completed, i.e., when the signal DP indicates that there is no data, the control unit 118 changes the state to the data output state S6 in accordance with the signal SD to issue the signal DOE to the output unit 124 so that the data stored in the buffer unit is outputted as the DATA1.
However, in this conventional receiving circuit, in a case where the clock signal is distorted due to the application of noise on the transmission path, a clock signal having a high clock rate would be determined to be inputted. When there is inputted to the receiving circuit such a clock signal having a shorter clock pulse than a width of the clock pulse contained in the normal clock signal, the control circuit 118 transits to an abnormal state so that the operation is in a fault state. In this case, flip-flop circuits needs to be reset, and unless the flip-flop circuit are not reset the control unit is not recovered to the normal state.